The present invention relates to an apparatus for reducing a sampling frequency. The major applications of the present invention are in a trans-multiplexer for converting a frequency-division-multiplexed-signal (FDM) to a pulse-code-modulation-signal (PCM), and carrier-frequency terminal equipment for distributing an FDM signal to each individual channel. According to the present invention, a part of the narrow band signal, for instance, a single channel signal, is derived from a wide band FDM signal with low frequency sampling signals which correspond to said narrow band signal.
A heterodyne frequency conversion system for deriving a single channel signal from an FDM signal is known, and lately, a discrete Fourier transform system for deriving said single channel signal from an FDM signal has been proposed. The present invention relates to an improvement of the discrete Fourier transform system.
According to a prior discrete Fourier transform system for reducing a sampling frequency, for instance, a part of the frequency band of an SSB.FDM signal, is picked up and the sampling frequency is then reduced. In this case, the derived frequency band must be less than half of the reduced sampling pulse frequency. In that system, the restriction of the input signal frequency band is performed by using a digital filter which directly processes the sampled signal on the time axis of the input signal, or by using an another digital filter which processes first the input signal on the frequency axis through the discrete Fourier transform (DFT) and then provides the time axis signal through the inverse discrete Fourier transform (IDFT). The process of the convolution of the input signal and the impulse response of the filter on the time axis is the same as the product of those two signals on the frequency axis.
Accordingly, the periodic convolution or the filtering can be performed by obtaining the product of the input signal and the impulse response on the frequency axis through the discrete Fourier transform (DFT), and providing the time axis signal from said product through the inverse discrete Fourier transform (IDFT).
FIG. 2 shows the convolution of two sampling signals, in which FIG. 2(a) shows the input signal and has G number of pulses (G=21 in the figure). FIG. 2(b) shows the impulse response of a filter and has F number of sampling pulses (F=3 in the figure), and FIG. 2(c) shows the result of the convolution, that is to say, FIG. 2(c) is the filter response of the input signal shown in FIG. 2(a) and has G+F-1 number of sampling pulses of (G+F-1=21+3-1=23). It should be noted from FIG. 2 that the result of the convolution has the number of sampling pulses more than the input signals by the (F-1) number of pulses, which is the number of the filter response minus one.
FIG. 3 shows the periodic convolution through discrete Fourier transform (DFT). FIG. 3(a) shows the periodic signal in which the signal in FIG. 2(a) repeats with the period of G sampling pulses, FIG. 3(b) is the periodic signal in which the signal in FIG. 2(b) repeats with the period of G sampling pulses. FIG. 3(c) is the convolution of the signals of FIG. 3(a) and FIG. 3(b). In FIG. 3(c), the portion with the hatching shows the interference portion due to the periodic signals of the signals in FIG. 3(a) and FIG. 3(b), and the other portions without hatching are the same as FIG. 2(c).
It should be noted from FIG. 3 that the processing of a non-periodic random signal shown in FIG. 2 by a filter through the discrete Fourier transform(DFT) provides an output which has an effective portion and a non-effective portion due to the effects of interference. In the embodiment, the effective portion is G-F+1=21-3+1=19, and the non-effective portion is F-1=3-1=2.
When complete filtering is desired for a random signal, two convolution circuits, each of which utilizes a DFT circuit, must be utilized and output signals of those two circuits must be connected. FIG. 4 shows that connection.
FIG. 4(a) shows the time that the input signal exists, and it should be noted that the input signal exists always as shown in the figure. As shown in FIG. 4(b), a part of said input signal is applied to the first system and is applied to the DFT circuit of the first system, in which the symbol (d) shows the delay time for the signal processing. The first system provides the output signal as shown in FIG. 4(d), after the predetermined processing time (d). Said output signal has an effective portion and a non-effective portion due to interference as mentioned above. A similar discussion is possible for the second system; the input signal is shown in FIG. 4(c) and the output signal is shown in FIG. 4(e). By connecting those two output signals (FIG. 4(d) and FIG. 4(e)), the complete output signal shown in FIG. 4(f) is obtained, in which (I) and (II) show the outputs from the system 1 and the system 2, respectively.
FIG. 1 shows the block-diagram of a prior sampling frequency reduction apparatus which utilizes a Fourier transform in accordance with the above conditions. In FIG. 1, the reference numeral 1 is the input terminal. The band-width of the input signal applied to the input terminal 1 is restricted to f.sub.B (H.sub.z) and said input signal is sampled at the sampling frequency 2f.sub.B (H.sub.z), and the input signal is in the form shown in FIG. 2(a). 2 and 3 are the discrete Fourier transform circuits for carrying out the discrete Fourier transform (DFT) with the unit of G number of sampling pulses, 4 and 5 are multiplexers, 6 is a memory having G sampling values which are obtained by sampling the impulse response h(t) of the F samples of the filter with the sampling frequency 2f.sub.B, and performing G point discrete Fourier transform. Said memory can be implemented by the combination of a battery and a potentiometer since said G sampling values are fixed for a predetermined filter. 7 and 8 are inverse discrete Fourier transform circuits (IDFT) each of which performs G points inverse Fourier transform. 9 is a switch for alternately providing the outputs of the circuits 7 and 8, 10 is the circuits for thinning out the pulses for deriving a single pulse from the continuous N pulses, and 11 is an output terminal. Between G and F, the relationship G&gt;2F must be satisfied. In FIG. 1, the portions (I) and (II) surrounded by a dotted line show the first system and the second system, respectively.
Nextly, at the operation of FIG. 1, the input of the thin out circuit 10 is mentioned below in accordance with FIG. 4. As described before, the signal at the terminal 1 has the duration time as shown in FIG. 4(a). Of the signal in FIG. 4(a), the portion shown in FIG. 4(b) is processed by the DFT circuit 2, and the portion shown in FIG. 4(c) is processed by the DFT circuit 3. The output signal processed by the DFT circuit 2 is further processed by being multiplied by the response of the filter in the multiplexer 4, and is processed by the inverse discrete Fourier transform circuit (IDFT) 7, and the output signal of the circuit 7 is obtained with some delay time for the signal processing. The duration time of said output signal of the IDFT circuit 7 is shown in FIG. 4(d). And said output signal has an effective output and a non-effective output due to the interference mentioned in accordance with FIG. 2 and FIG. 3. Also, the signal processed by the other DFT circuit 3 is provided from the output of the IDFT circuit 8 with some delay time and, the duration time of which is shown in FIG. 4(e). The switch 9 derives only the effective portions of the two systems, and the output of the switch 9 is shown in FIG. 4(f). The control signal for control of the operation of the switch 9 appears at the instant of input signal end delayed by aforementioned processing period, as apparent from FIG. 4(f ).
Now, it is assumed that the apparatus in FIG. 1 is utilized for deriving an output signal having the band-width f.sub.B /N from the frequency division signal (FDM) having the band-width f.sub.B, where N is an integer and is the same as the number of multiplexed channels of a FDM system. In this case, the transfer function which is applied to the multiplyers 4 and 5 from the memory 6 has the characteristics of bandpass filter with the bandwidth f.sub.B /N. Accordingly, the output of the switch 9 has a sampling frequency f.sub.B and a bandwidth less than f.sub.B /N. By the way, it should be noted that the sampling frequency for the signal of the bandwidth less than f.sub.B /N can be only 2f.sub.B /N from the well-known sampling theory. Accordingly, in view of the sampling frequency, the output signal of the switch 9 has too many samples. The thin out circuit 10 thins out the samples for every N samples and provides signal sampled at frequency of 2f.sub.B /N which corresponds to the signal with the bandwidth f.sub.B /N.
In other words, the thin out circuit 10 re-samples the fine sampled input signal to provide the coarse sampled output signal.
However, the prior circuit shown in FIG. 1 has the disadvantage that it must process too many sampled signals. In other words, although the G points IDFT circuits 7 and 8 provide G outputs, respectively, only G/N of them are actually utilized in the successive circuit. Therefore, when the value N is large, the unnecessary process or calculation in the IDFT circuits must be extravagant.